 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SN54/74LS95B 4-BIT SHIFT REGISTER The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. The LS95B is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. 4-BIT SHIFT REGISTER LOW POWER SCHOTTKY * * * * * Synchronous, Expandable Shift Right Synchronous Shift Left Capability Synchronous Parallel Load Separate Shift and Load Clock Inputs Input Clamp Diodes Limit High Speed Termination Effects 14 1 J SUFFIX CERAMIC CASE 632-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 Q0 13 Q1 12 Q2 11 Q3 10 CP1 9 CP2 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 1 N SUFFIX PLASTIC CASE 646-06 VCC = PIN 14 GND = PIN 7 1 DS 2 P0 3 P1 4 P2 5 P3 6 S 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC S DS P0 - P3 CP1 CP2 Q0 - Q3 Mode Control Input Serial Data Input Parallel Data Inputs Serial Clock (Active LOW Going Edge) Input Parallel Clock (Active LOW Going Edge) Input Parallel Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-1 SN54/74LS95B LOGIC DIAGRAM P0 6 2 P1 3 P2 4 P3 5 S 1 DS 9 CP1 8 CP2 R R R R S VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q 13 S Q 12 S Q 11 S Q 10 Q0 Q1 Q2 Q3 FUNCTIONAL DESCRIPTION The LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. It has a Serial (DS) and four Parallel (P0 - P3) Data inputs and four Parallel Data outputs (Q0 - Q3). The serial or parallel mode of operation is controlled by a Mode Control input (S) and two Clock Inputs (CP1) and (CP2). The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected clock input. When the Mode Control input (S) is HIGH, CP2 is enabled. A HIGH to LOW transition on enabled CP2 transfers parallel data from the P0 - P3 inputs to the Q0 - Q3 outputs. When the Mode Control input (S) is LOW, CP1 is enabled. A HIGH to LOW transition on enabled CP1 transfers the data from Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1 to Q2, and Q2 to Q3 respectively (right-shift). A left-shift is accomplished by externally connecting Q3 to P2, Q2 to P1, and Q1 to P0, and operating the LS95B in the parallel mode (S = HIGH). For normal operation, S should only change states when both Clock inputs are LOW. However, changing S from LOW to HIGH while CP2 is HIGH, or changing S from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes on the register outputs. MODE SELECT -- TRUTH TABLE INPUTS OPERATING MODE S Shift Parallel Load L L H X L L H H L L H H L L L L H H H H CP1 CP2 X X DS I h X X X X X X X X X Pn X X Pn X X X X X X X X Q0 L H P0 Q1 q0 q0 P1 Q2 q1 q1 P2 Q3 q2 q2 P3 OUTPUTS Mode Change No Change No Change No Change Undetermined Undetermined No Change Undetermined No Change L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition. h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition. Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn = HIGH to LOW clock transition. FAST AND LS TTL DATA 5-2 SN54/74LS95B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input HIGH Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 -100 21 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPLH tPHL Parameter P Maximum Clock Frequency CP to Output 21 32 ns Min 25 Typ 36 18 27 Max Unit Ui MHz ns VCC = 5.0 V 50 CL = 15 pF Test C di i T Conditions AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tW ts th ts th CP Pulse Width Data Setup Time Data Hold Time Mode Control Setup Time Mode Control Hold Time Parameter P Min 20 20 20 20 20 Typ Max Unit Ui ns ns ns ns ns VCC = 5.0 V 50 Test C di i T Conditions FAST AND LS TTL DATA 5-3 SN54/74LS95B DESCRIPTION OF TERMS SETUP TIME(ts) --is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. D 1.3 V th(L) ts(L) 1.3 V 1.3 V 1.3 V th(H) *The Data Input is (DS for CP1) or (Pn for CP2). ts(H) 1.3 V 1.3 V l/fmax tW 1.3 V CP1 or CP2 tPHL Q 1.3 V tPLH 1.3 V Figure 1 (H L ONLY) (L H ONLY) (L H ONLY) S ts(H) ts(L) 1.3 V 1.3 V STABLE ts(H) th(L OR H) 1.3 V 1.3 V th(L) CP1 1.3 V tW 1.3 V ts(L) 1.3 V tW ts(H) ts(L) th(H) CP2 1.3 V 1.3 V 1.3 V Figure 2 FAST AND LS TTL DATA 5-4 |
Price & Availability of SN5474LS95B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |